Body biasing is a disruptive 22FDX® feature enabling post silicon adaption of transistor threshold voltages. Racyics’ Adaptive Body Biasing (ABB) technology provides reliable and predictable ultra-low voltage (ULV) operation down to 0.4V, compensating process, supply voltage and temperature variations (PVT) to guarantee timing and power with high yield.
Key Facts
- Comprehensive ABB platform for ULP and high-performance applications
- ABB generator, standard cells, SRAM
- Up to 9X performance (versus no-bias)
- 75% leakage reduction (versus static bias trimming)
- Corner tightening and ABB-aware implementation for improved PPA
- Guaranteed performance and power
- Easy-to use turnkey ABB solution based on standard design flow and sign-off
- Silicon-proven
- Free evaluation kit via sales@racyics.com available now!
Product Sheets
| ABB IP Platform | Racyics ABB IP Platfrom › |
| Standard Cell Libraries incl. PMK | Racyics Standard Cell Libs › |
| SRAM | Racyics DualRail SRAM › |
| ABB Generator IP | Racyics ABB Generator IP › |
| IO Library* | Racyics IO Library › |
| ULV Clock Generator 20 Mhz up to 1 GHz (ADPLL)* | Racyics ULV Clock Generator 20MHz to 1GHz› |
| ULP 10 MHz Reference Clock Generator (ADFLL)* | Racyics ULP 10MHz Clock Generator› |
| * Additional IP for glue-less interfacing to ULV Racyics® ABB IP Platform | |
