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Job Offer: SoC Physical Design Engineer
Extending our international team, we are looking for a SoC Physical Design Engineer (Entry-Level).
Job Description:
- Contribute to physical design, implementation and verification of complex digital and mixed signal SoCs
- Implementation according to customer requirements using state-of-the-art EDA tools and flows
- Support individual steps in RTL2GDS flow like Synthesis, P&R, Physical Verification, EMIR, Equivalence Check or Static Timing Analysis
- Address challenges in designing SoCs in leading edge Technologies
- Contribute to methodology developments with proposals and implementation of flow and methodology enhancements
Requirements:
- Bachelor’s/Master’s Degree in Electrical Engineering or Information Technology or similar required
- Experience in Physical Implementation in leading edge CMOS and/or FDSOI technologies is a plus
- Basic knowledge of state-of-the-art synthesis, P&R and verification tools from Cadence, Synopsys, Ansys and Mentor
- Basic knowledge in Programming in TCL, Perl or Python is a plus
- Knowledge in timing modelling and timing analysis for digital designs is a plus
- Basic knowledge in RTL Design
- Self-driven and hands-on way of working
- Strong analytical and solution-oriented thinking
- Good written and oral communication skills in English
- Team-player
Location:
Dresden, Germany
Duisburg, Germany
Frankfurt/Main, Germany
Employment Type:
Full-time (up to 40 hours per week)
Send us a mail with your CV incl. your certificates, transcripts etc. attached to jobs@racyics.com. Please mind that we can only consider attachments in PDF format.