Racyics GmbH
  • Services
    • Design Services
    • Foundry Access
    • Custom IP
    • Turnkey Solutions
  • About Us
    • Overview
    • Research Projects
  • Products
    • Racyics® ABX Platform
    • makeChip
  • News
    • Archive
  • Career
    • Jobs
  • Contact Us
‹ Previous PostRacyics at Intap Pitch & Match 2019
Next Post ›Racyics at embedded world 2019 in Nuremberg

Home » News » Archive » General News » Racyics extends its Silicon Proven ABX Platform Portfolio

Racyics extends its Silicon Proven ABX Platform Portfolio


Dresden, Germany − February 25, 2019 −

Clock generation is an essential part of every SoC. That’s why Racyics extends its silicon proven, fully Adaptive Body Bias enabled IP offering by adding 

  • an Ultra-Low-Voltage fast lock-in ADPLL enabled for ABB and DVFS; supply voltage from 0.4V to 0.8V with up to 1 GHz and power consumption as low as 100 µW at 100 MHz; 0.5V operation.
  • a 10 MHz, 5µW Ultra-Low-Power ADFLL Clock generator with flexible reference input clock from 32kHz to 1 MHz; suitable for Racyics’ Adaptive Body Bias solution .

Get all the information about our ABX Platform!


Related posts from the category General News
  • arrow_forwardRacyics at the Bonding Fair, Dresden
  • arrow_forwardTogether for an open-minded Saxony
  • arrow_forwardembedded world 2017
News
  • 2022
  • 2021
  • 2020
  • 2019
  • 2018
  • 2017
  • 2016
  • 2015
  • 2014
  • 2013
  • 2011
Tags
ABX Platform General News Globalfoundries makeChip Press Releases
Contact

Racyics GmbH
Bergstraße 56
01069 Dresden
Germany

phone+49 (0)351 41 88 72-0print+49 (0)351 41 88 72-99mailcontact@racyics.comlanguagewww.racyics.com

  • Services
    • Design Services
    • Foundry Access
    • Custom IP
    • Turnkey Solutions
  • About Us
    • Overview
    • Research Projects
  • Products
    • Racyics® ABX Platform
    • makeChip
  • News
    • Archive
  • Career
    • Jobs
  • Contact Us
© 2023 Racyics GmbH. All rights reserved.
  • Imprint
  • Disclaimer
  • Data Protection
keyboard_arrow_up