Extending our young team, we are looking for a Digital Design Engineer (Entry-Level).
Job Description:
- Support architecture definition of digital blocks according to customer specification
- Support RTL design (VHDL, Verilog) of digital blocks and their system level integration
- Closely work together with RTL2GDS flow experts to optimize digital blocks and support block implementation
- Support chip and block level functional verification
- Implement and maintain regression setups for verification
- Create verification plans and develop verification environments based on Unified Verification Methodology (UVM)
- Support product qualification, testing and ramp-up
- Support methodology team with proposals and implementation of flow and methodology enhancements
Requirements:
- Bachelor’s/Master’s Degree in Electrical Engineering or Information Technology or similar required
- Basic knowledge of hardware description languages (VHDL, Verilog) and System Verilog
- Knowledge about synthesis constraints (SDC) and UPF
- Understanding of UVW/OVM concepts and usage or strong motivation to learn concepts for state of the art verification
- Experience in functional verification and creating test concepts and verification environments is a plus
- Good communication and negotiation skills
- Self-driven and hands-on way of working
- Good written and oral communication skills in English
- Team-player
Location:
Racyics GmbH, Bergstraße 56, 01069 Dresden, Germany
Employment Type:
Full-time (40 hours per week)