Job Offer: Digital Design Engineer

Extending our international team, we are looking for a Digital Design Engineer (Entry-Level).

Job Description:

• Support architecture definition of digital blocks according to customer specification
• Support RTL design (VHDL, Verilog) of digital blocks and their system level integration
• Closely work together with RTL2GDS flow experts to optimize digital blocks and support block implementation
• Support chip and block level functional verification
• Implement and maintain regression setups for verification
• Create verification plans and develop verification environments based on Unified Verification Methodology (UVM)
• Support product qualification, testing and ramp-up
• Support methodology team with proposals and implementation of flow and methodology enhancements

Requirements:

• Bachelor’s/Master’s Degree in Electrical Engineering or Information Technology or similar required
• Basic knowledge of hardware description languages (VHDL, Verilog) and System Verilog
• Knowledge about synthesis constraints (SDC) and UPF
• Understanding of UVW/OVM concepts and usage or strong motivation to learn concepts for state of the art verification
• Experience in functional verification and creating test concepts and verification environments is a plus
• Self-driven and hands-on way of working
• Good written and oral communication skills in English
• Team-player

Location:

Dresden, Germany

Employment Type:

Full-time (up to 40 hours per week)

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Send us a mail with your CV incl. your certificates, transcripts etc. attached to jobs@racyics.com. Please mind that we can only consider attachments in PDF format.