Introduction to Racyics’ Design for Test (DFT) Engineering Line 

In the complex world of IC design, ensuring the reliability and functionality of our ICs is a multifaceted challenge. Among the key strategies employed to tackle these challenges, Design For Testability (Hashtag#DFT) stands out as an essential component in the IC design process.

DFT is a set of techniques and methodologies carefully integrated into the design phase, with the primary goal to make sure that ICs are built in a way that makes effective and efficient testing possible – not just during production, but also during their entire lifetime.

To achieve this, our Racyics DFT department works closely with customers, our other departments and in-house lab to develop appropriately sized DFT concepts for mixed signal ASICs that consider complexity, functional safety, low power and cost. Here is an overview of typical test structures that our DFT team applies:

➕ Full hierarchical Scan Insertion including Scan Compression and On-Chip Clock Controlling
➕ Low power scan in close collaboration with our EMIR analysis engineers
➕ Core Wrapping (IEEE 1500)
➕ Logic Built-in Self Testing (LBIST)
➕ Boundary Scan (IEEE 1149.1 also known as JTAG)
➕ Memory BIST including Built-In Self Repair (BISR)
➕ IJTAG (IEEE 1687)
➕ Mission Mode Controller to run Built-in Self-tests during Mission Mode
➕ High Speed Scan Busses (Streaming Fabrics)
➕ Testing of 3D Stacked ICs (IEEE 1838)
➕ Pattern retargeting and generation of test patterns for analog-mixed-signal components
➕ Post-Silicon test pattern diagnostics and yield Improvements

By incorporating DFT techniques from the earliest stages of IC design, our engineers create chips that not only perform their intended functions but also possess the robustness and reliability required in a wide range of applications – from consumer electronics to ISO 26262 projects in automotive and critical infrastructure.

Sounds interesting to you? We are happy to provide more information on how we can help you with your project!