Racyics is going to Design and Reuse IP-SoC Silicon Valley 2025!

Racyics is heading to Silicon Valley to share our latest IP offering, makeChip design platform and IP design services.​

Our Director Design Service, Florian Bilstein, will be presenting: makeChip: an accessible, cost-effective, and cloud-based Chip Design Platform
Time: 3:00–4:15 PM​
Room: 2​
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See live demonstrators of Racyics 22FDX®IP. ​
Location: Hyatt Regency Santa Clara, 5101 Great America Parkway – Santa Clara, CA ​
Date: April 24th, 2025​

​Two cool outtakes from our rich IP Catalogue:
Racyics ABX® IP leverages the full potential of 22FDX®​
o Tightening sign-off corners yielding superior PPA​
o  Enabling ultra-low voltage operation​
o  Controlling leakage at 150°C​
o  Inter-operable with both Racyics and 3rd party std cells​
o  Single-rail, back-bias capable 1P and 2P SRAMs and mask ROM​

Racyics ULP IP provides comprehensive power supply and clocking for edge devices with low-voltage, low-power and highest efficiency.​
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We’re looking forward to meeting you, hearing about your design challenges, and exploring how we can support your next chip design!​