Racyics presenting at Workshop on Test Methods and Reliability of Circuits and Systems

Racyics has presented our student’s master thesis at the 36. ITG / GMM / GI -Workshop on Test Methods and Reliability of Circuits and Systems organized by Technische Universität Darmstadt and Siemens EDA, where we showcased his master’s thesis research about “ATPG-Based Die-to-Die Interconnect Fault Coverage in 3D Stacked ICs“.

Addressing manufacturing defects such as shorts among micro-bump pairs or open circuits, which pose a severe design challenge due to the large number of interconnects and their miniature size in 3D stacked ICs, his research offers valuable insights into improving reliability and testing.

As ATE-based test methods for post-stack testing of die-to-die interconnects (including mid-bond, full-bond and packaged tests) become crucial, his findings provide a foundation for enhancing the efficacy of these testing approaches.

Our ATPG-based approach focuses on fault modeling that accurately abstracts the physical short defects in interconnects between interconnect pairs as well as, interconnect open defects. This method aims to streamline the test patterns and reduce the time required for testing while achieving comprehensive fault coverage.

The Racyics team as well as the DFT line are eagerly excited to continue this productive discourse within the DFT community. Furthermore, we are looking forward to the next workshop, where we hope to deepening our connections and create some more new professional relationships.