Racyics at ISCAS 2019
Dresden, Germany / Sapporo, Japan − May 23, 2019 −
Racyics at ISCAS 2019
We are presenting our ABB-enabled, ultra-low voltage All-Digital PLL clock generator for highly energy efficient Systems on Chip at the IEEE International Symposium on Circuits and Systems (ISCAS) 2019 in Sapporo, Hokkaido, Japan!
The Racyics® ADPLL clock generator is based on a DCO with an inherently linear and offset-free tuning characteristic. Only one measurement is needed to calculate the tuning value for any target frequency, allowing both short lock-in times and fast frequency changes during operation without requiring additional DCO instances or dividers. ABB improves the energy efficiency of the clock generator and the output clock characteristics especially at low supply voltages by compensating PVT variation.
For more information see https://ieeexplore.ieee.org/document/8702109
About Racyics® ABB IP Platform
Body biasing is a disruptive 22FDX® feature enabling post silicon adaption of transistor threshold voltages. Racyics® Adaptive Body Biasing (ABB) technology provides reliable and predictable ultra-low voltage (ULV) operation down to 0.4V, compensating process, supply voltage and temperature variations (PVT) to guarantee timing and power with high yield.
For more information see ABX Platform
About ISCAS
ISCAS is the flagship conference of the IEEE Circuits and Systems Society and the world’s premier networking forum for leading researchers in the highly active fields of theory, design and implementation of circuits and systems.
For more information see https://www.iscas2019.org/