Racyics at embedded world Conference 2026

Racyics will be present at the embedded world Conference 2026, where Alexander Persicke will give a presentation on wafer-level testing for chiplet-based systems.

In his talk, “Wafer-Level Test Concept for the Universal Chiplet Interconnect Express (UCIe) Interface,” he will present a test approach for high-speed die-to-die communication. The focus will be on developing robust and practical strategies to support reliable chiplet integration.

Chiplet-based systems require Known Good Dies (KGDs) before assembly, as defective chiplets can significantly reduce yield and increase costs. A reliable wafer-level test strategy is therefore essential, especially for high-speed interfaces such as UCIe.

The presentation introduces a pre-package test concept for the UCIe interface. It translates the UCIe architecture into test domains that can be applied at wafer level using established and manufacturable methods. The approach combines logic testing, loopback-based built-in self-test (BIST), and dedicated tests for critical analog components.

Session Details

Date: Tuesday, 10 March 2026
Time: 14:45–15:15
Location: Room Budapest
Session: Chiplets – Certification, Validation & Test (Session 4.2, powered by UCIe)

Racyics will also be present at the exhibition and welcomes visitors to continue the discussion at the company’s booth.